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Flash Memory Controller
Flash address and data values are communicated over system busses. Flash controls are managed via
registers mapped onto the IP-bus space. User access to program/erase functions is via dedicated ROM
function calls. Direct access to flash controller registers is disallowed.
6.1.2
Features
Features of the on-chip flash memory include:
? 4K-deep by 32-bit main array (16 KB total)
? Page erase size = 512 bytes
? Security lockout
? Protection against accidental programming/erase operations
? Program, erase and mass-erase procedures can be performed using pre-programmed ROM
routines.
6.2
Theory of operation
Flash memory is nonvolatile and is ideal for single-supply applications allowing for field reprogramming
with no need for external, high-voltage sources for programming or erase operations. Contents are retained
for an extended period of time over 100 years under nominal conditions.
Contents of flash memory can be read randomly, just like RAM. Array read-access time is one bus cycle
for bytes, aligned words and aligned double-words. Unlike random access memory, flash memory cannot
simply be written with a desired value. It must first be “erased” and “programmed.” For flash memory, an
erased bit reads 1 and a programmed bit reads 0. Once programmed to 0, a bit cell remains in that state
until erased again. A bit cell cannot be “programmed” to change from 0 to 1.
It is not possible to read from flash memory while it is being erased or programmed.
Bit cells can be erased/programmed a finite number of times before data integrity issues begin to occur.
Nevertheless minimum number of erase/program cycles can exceed 20,000 under nominal conditions.
NOTE
A flash block address must be in the erased state before being programmed.
Cumulative programming of bits within a flash block address is not allowed
except for status field updates required in EEPROM emulation applications.
The flash hard block has a number of control signals associated with programming and erase operations.
These must be sequenced over time and in a specified manner in order to erase and subsequently program
flash memory. Internally generated, high voltages are applied for specific periods of time which must not
be exceeded.
The hardware wrapper for flash memory provides rudimentary interlocks and safeguards, as well as some
strobe generation. Higher-level intelligence is provided via canned ROM routines for basic flash
operations.
All program erase operations must be performed using ROM routines executed while the CPU is in
Supervisor mode. A special trap function (call_trap) is supplied which places the CPU in the Supervisor
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
62
Freescale Semiconductor, Inc.
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